`timescale 1ns/1ns
module tb_get_instruct();
reg sys_clk;
reg sys_rst_n;
reg get_inst_en;
reg [15:0] ip;	
wire decode_en;
wire [15:0] instruct_code;

wire [15:0] ip_buf;
wire [15:0] instruct_code_wire;
wire rd_en;
wire rd_en_d1;
wire rd_en_d2;

reg [9:0] cnt;

assign ip_buf = get_instruct_inst.ip_buf;
assign instruct_code_wire = get_instruct_inst.instruct_code_wire;
assign rd_en = get_instruct_inst.rd_en;
assign rd_en_d1 = get_instruct_inst.rd_en_d1;
assign rd_en_d2 = get_instruct_inst.rd_en_d2;

initial
begin
	sys_clk = 1'b1;
	sys_rst_n <= 1'b0;
#60
	sys_rst_n <= 1'b1;
end

always #10 sys_clk = ~sys_clk;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		cnt <= 10'd0;
	else if (cnt < 10'd20)
		cnt <= cnt + 10'd1;
	else
		cnt <= cnt;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
	begin
		get_inst_en <= 1'b0;
		ip <= 16'h0000;
	end
	else if (cnt == 10'd3)
	begin
		get_inst_en <= 1'b1;
		ip <= 16'h0002;
	end
	else
	begin
		get_inst_en <= 1'b0;
		ip <= 16'h0000;
	end

get_instruct get_instruct_inst(
	.sys_clk(sys_clk),
	.sys_rst_n(sys_rst_n),
	.get_inst_en(get_inst_en),
	.ip(ip),
	.decode_en(decode_en),
	.instruct_code(instruct_code)
);

endmodule